Adequate on-chip ESD (electrostatic discharge) protection design has emerged as a major challenge for mixed-signal (M-S), RF, and high-pin-count ICs as fabrication technologies shrink. This challenge is mainly due to parasitic effects induced by, and the large areas of silicon consumed by, known ESD protection structures (hereinafter commonly referred to simply as xe2x80x9cESD structuresxe2x80x9d). ESD structures inevitably produce parasitics, e.g., capacitances and noises, resulting in performance degradation of the core IC circuit the ESD structures are designed to protect. Traditionally, a complete ESD protection scheme uses multiple ESD circuits and structures for each I/O pad to survive ESD pulses of all polarities, i.e., I/O to VDD positively (PD) and negatively (ND), I/O to VSS positively (PS) and negatively (NS), as well as VDD to Vss positively (DS) and, in rare cases, VSS to VDD positively (SD). In these circumstances, the influence of known ESD structures on the core IC circuit can become intolerable to parasitic-sensitive M-S/RF ICs. For example, significant degradation in RF ICs in eighteen-hundredths micron technology (0.18 xcexcm) using NMOS ESD structures has been reported (xe2x88x9230% in general and xe2x88x925% in noise factor) as set forth in Ke Gong, Haigang Feng, Rouying Zhan and Albert Z. Wang, xe2x80x9cA Study of Parasitic Effects of ESD Protection on RF ICsxe2x80x9d, IEEE Trans. Microwave Theory and Techniques, Vol. 50, No. 1, Jan. 2002, pp.393-402.
Also, ESD devices consume large areas of silicon on the chip, especially in M-S/RF ICs which demand high ESD protection or high-pin-count chips using a large number of ESD units. For example, up to 30% of the silicon substrate is used for NMOS ESD devices in a transceiver chip as set forth in F. Hatori, S. Kousai and Y. Unekawa, xe2x80x9cShared Data Line Technique For Doubling The Data Transfer Rate Per Pin Of Differential Interfacesxe2x80x9d, Proc. IEEE Custom Integrated Circuits Conference, 2001, pp. 501-504.
Large ESD structures further make chip layout extremely difficult, often leading to pre-mature ESD failure. It is hence imperative to develop compact ESD structures that, while offering high ESD protection, produce little parasitic effect and consume small space on the chip, are layout-friendly, and can be placed underneath or surrounding bonding pads. It is further desirable that such ESD structures provide symmetrical performance characteristics, as well as uniform current and thermal distribution properties, while providing all direction ESD protection with a single structure to make chip layout easier.
An all-direction ESD structure of similar function but different design has been disclosed to the U.S. Patent and Trademark Office by the same inventor in co-pending application Ser. No. 09/450,576, filed Nov. 30, 1999, which is incorporated by reference herein in its entirety.
The present invention provides an all-mode, pad-oriented, compact, active ESD protection structure. A substantially bilaterally symmetrical layout design, sometimes referred to herein as xe2x80x9cquasi-symmetricalxe2x80x9d, is provided which eliminates possible localized junction damages and improves ESD robustness and provides uniform current and thermal distribution. The ESD structure can provide a low holding voltage ( less than 2V), low discharge impedance (xcx9cxcexa9), fast response time (xcx9c0.18 ns) and low parasitics. The structure of the present invention can be placed underneath or surrounding bonding pads and consumes little silicon. Structures according to the present invention can pass 14 KV HBM (human body model) and 15 KV air-gap IEC (International Electrotechnical Commission) ESD zapping tests.
The present invention is particularly suitable for multiple-supply, mixed-signal (M-S), parasitic-sensitive, RF, and high-pin-count ICs.
One embodiment of the invention includes a substantially bilaterally symmetrical layout of N+ and P+ diffusion and P well areas occupying each bonding pad area in an IC. As noted, the substantially bilaterally symmetrical layout taught herein may also sometimes be called a xe2x80x9cquasi-symmetricalxe2x80x9d layout. In either case the terms are meant to distinguish from a radially symmetrical layout which could include inherent disadvantages as further discussed below. Words of degree, such as xe2x80x9caboutxe2x80x9d, xe2x80x9csubstantiallyxe2x80x9d, and the like are used herein in the sense of xe2x80x9cat, or nearly at, when given the manufacturing and material limitations inherent in the stated circumstancesxe2x80x9d and are used to prevent the unscrupulous infringer from unfairly taking advantage of the invention disclosure where exact figures or absolutes are stated as an aid to understanding the invention.
An example of an ESD structure layout according to one aspect of the present invention in an N-epi-layer P well process technology is given, although it will be appreciated by the person having ordinary skill in the art that other variants may be used, e.g., a P epi-layer twin-well (P-well and N-well) process with an intervening N isolation layer. The N-epi-layer P well example, as illustrated in FIG. 1 includes a central construction having a first P center well that has a first center P+ diffusion partially surrounded over first and second areas, such as about xe2x88x9290 degree arcs, or quarter lengths, of its circumference by first and second opposing N+ diffusion areas, respectively. The first and second N+ diffusions are separated by first and second, e.g. about xe2x88x9290 degree, areas of Field Oxide (Fox) insulation. The entire central construction is isolated by a surrounding moat of Field Oxide insulation which includes the first and second areas of Field Oxide insulation.
A second level construction surrounding the central construction outside of the Field Oxide insulation moat includes second and third P-wells, each of which has third and fourth N+ diffusion areas occupying the areas surrounding the opposing about xe2x88x9290 degree areas of Field Oxide insulation of the central construction. Distal from, and adjacent to, each of the third and fourth N+ diffusion areas of the second level are P+ diffusion first and second half rings, also within said second and third P-wells, and separated by areas of Field Oxide insulation connected to the Field Oxide insulation moat. Each half ring surrounds about half of the central construction including one central construction N+ diffusion and one about xe2x88x9290 degree area of Field Oxide insulation. An unbroken protection ring or rings of either or both conductive types (N and P) may surround the second and third P-wells and be separated therefrom by a ring of Field Oxide insulation connected to the Field Oxide insulation areas of the central and second level constructions.
The design, or layout, may be in the form of a circular layout where all wells and rings have a substantially constant radius, i.e. being rounded. Alternatively, the design may be in the form of a more squared layout. In this embodiment, it is preferred that all wells and rings have at least an outside, or distal, edge of a bend between any two straight edges thereof rounded to promote even, or uniform, current and thermal distribution.
The invention may provide at least 6 one-direction SCR (silicon controlled rectifier) devices, or essentially 3 two-direction SCR devices, thereby providing a fast, low impedance, active discharging path in each ESD stressing mode, i.e. ND, PD, PS, NS, DS and SD modes. The device can be made compact and will have low parasitic effects.